1. Field of the Invention
The present invention relates to a phase comparator and a semiconductor integrated circuit, and more particularly, to a phase comparator for a delay locked loop (DLL) circuit and a semiconductor integrated circuit employing the DLL circuit.
2. Description of the Related Art
Recently, the operating speeds of semiconductor integrated circuits have increased, and the circuit scale thereof has become large. Further, it has become necessary to supply a synchronized signal (phase synchronized clock signal) to a specific circuit in a large scale semiconductor integrated circuit.
Namely, recent high-speed, highly-integrated semiconductor circuits need phase-synchronized clock signals. For example, synchronous DRAMs (SDRAMs) employ a DLL (Delay Locked Loop) circuit that generates an internal clock signal in synchronization with an externally supplied clock signal and supplies the internal clock signal to output buffer circuits. As the frequency of the external clock signal increases, a phase difference between the external and internal clock signals increases. Even if the frequency of the external clock signal is high, the DLL circuit must correctly compare the phases of the external and internal clock signals with each other and synchronize the internal clock signal with the external clock signal.
Recent MPUs and memory devices such as SDRAMs operate at a speed of 100 MHz or faster. These devices employ the DLL circuit to lock the phase of an internal clock signal with that of an externally supplied clock signal, to thereby absorb a delay caused by internal clock lines and stabilize an accessing time.
When the frequencies of the external and internal clock signals are high, it is difficult for the DLL circuit to compare the phases of the signals with each other. To cope with this problem, a prior art has proposed a phase locked loop (PLL) circuit that divides the frequencies of the external and internal clock signals at a given ratio and compares the phases of the frequency-divided clock signals with each other. This technique is disclosed in, for example, Japanese Unexamined Patent Publication (Kokai) Nos. 55-92042 and 56-61833.
The conventional PLL circuit and related DLL circuit and the problems thereof will be explained later in detail with reference to drawings.